This invention relates to an input/output architecture for a programmable logic device, and more particularly to a programmable logic device having a plurality of input/output regions, each capable of supporting input/output standards with different power requirements than the other regions.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output ("I/O") pins, with the connections of the pins to the interconnect structure also being programmable and being made through suitable I/O buffer circuitry.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor-transistor logic ("TTL"), in which a logical "high" signal was nominally at volts, while a logical "low" signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signalling schemes, such as LVTTL (Low Voltage TTL, which exists in a 3.3-volt version or a 2.5-volt version), PCI (Peripheral Component Interface, which requires a 3.3-volt power supply), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants), LVDS (Low Voltage Differential Signalling), and others. Not only might these signalling schemes use different voltage levels for a "high" signal, and therefore require different supply voltages (the power supply requirements for these various standards may be 5.0 volts, 3.3 volts, 2.7 volts, 2.5 volts, 1.8 volts or 1.5 volts), but some of them, such as GTL/GTL+, various variants of SSTL and HSTL, and other standards such as CTT, ECL and 3.3 V AGP, may require a source of reference voltage. Typically, like the supply voltage, reference voltage would be supplied externally, using one of the I/O pins.
Power for the circuitry on the programmable logic device is typically supplied by a power bus that extends over the entire device. Heretofore, that same power bus supplied power to all of the I/O circuitry as well. Similarly, if a reference voltage were needed, a reference voltage bus would be provided on the device to supply all of the circuitry that required the reference voltage.
There is no inherent reason why two or more different I/O standards could not be used on one programmable logic device, with some I/O pins driven by circuitry compatible with one standard and other I/O pins driven by circuitry compatible with a different standard. However, the known single supply voltage bus and single reference voltage bus (if multiple reference voltages are needed) would be unable to supply more than one such standard or, at best, would only be able to supply multiple standards all of which had the same power requirements.
It would be desirable to be able to provide a programmable logic device that programmably supports a plurality of I/O standards, at least two of those standards being supportable simultaneously.
It would further be desirable to be able to provide such a programmable logic device in which the plurality of I/O standards could have different power requirements which could be met simultaneously by the programmable logic device.